1. Field of the Invention
The present invention relates to a substrate processing method and apparatus, and more particularly to a substrate processing method and apparatus which is useful, for example, in the fields of LSI, displays and magnetic heads, and in the field of chip mounting thereof, for forming a metal film (interconnect material), such as a copper film, by plating a surface of a substrate having fine interconnect recesses (interconnect patterns) formed therein, and removing an extra metal film, thereby forming metal interconnects of a submicron to micron size.
2. Description of the Related Art
In recent years, instead of using aluminum or aluminum alloys as an interconnect material for forming electrical interconnects on a semiconductor substrate, there has been an eminent movement toward using copper (Cu) which has a low electric resistivity and high electromigration resistance. It is generally difficult with copper to form interconnects by anisotropic etching as practiced with aluminum. Accordingly, copper interconnects are generally formed by a so-called copper damascene technique, which comprises embedding of copper in fine recesses formed in a surface of a substrate. Known methods for forming such copper interconnects include CVD, sputtering and plating. According to any such method, a copper film is formed on almost an entire surface of a substrate, followed by removal of unnecessary copper by performing chemical-mechanical polishing (CMP).
FIGS. 1A through 1C illustrate, in sequence of process steps, a process for producing a substrate W having such copper interconnects, and FIG. 2 is a flow chart of the process. First, as shown in FIG. 1A, an insulating film (interlayer dielectric) 2, for example, an oxide film of SiO2 or a film of a low-k material, is deposited on a conductive layer 1a in which semiconductor devices are formed and which is formed on a semiconductor base 1. Fine interconnect recesses, such as fine holes (via holes) 3 and interconnect trenches 4, are formed in the insulating film 2 by performing a lithography/etching technique. Thereafter, a barrier layer 5 of TaN or the like is formed on an entire surface of the insulating film 2, and a seed layer 7, serving as an electric feeding layer during electroplating, is formed on the barrier layer 5. A substrate W having fine interconnect recesses formed in a surface thereof is thus prepared.
Then, as shown in FIG. 1B, copper plating of the surface of the substrate W is performed to fill the fine holes 3 and the interconnect trenches 4 with copper and, at the same time, deposit a copper film 6 on the insulating film 2 (step 1). At this stage, the copper film 6 is deposited on an entire surface of the substrate W including, besides a device-formation-region, an edge (bevel) portion which is an ineffective region. Further, a copper film can inevitably be formed on a back surface of the substrate W. Accordingly, the copper film deposited in the ineffective region, i.e. the edge (bevel) portion, of the substrate is removed, for example by etching, followed by cleaning and, if necessary, the back surface of the substrate is also cleaned (step 2). Further, according to necessity, the substrate W is subjected to annealing (heating) or infrared irradiation to grow and stabilize metal crystals of the copper film 6 (step 3).
Next, an extra or unnecessary copper film 6 and the barrier layer 5 on the insulating film 2 are removed by chemical-mechanical polishing (CMP) so as to make a surface of the copper film 6, filled in the fine holes 3 and the interconnect trenches 4, substantially flush with a surface of the insulating film 2. Interconnects, which are formed of the copper film 6, as shown in FIG. 1C, are thus formed (step 4). Front and back surfaces of the substrate, having the interconnects of copper film 6, are cleaned by using a combined chemical and physical means, for example a combination of a chemical and scrubbing, and rinsed (cleaned) with pure water, followed by spin-drying (step 5). The substrate after drying is then sent to a next process.
The above-described crystal stabilization processing is generally performed by heating the substrate in an inert gas atmosphere. In some cases, however, it is effective to allow the substrate to stand at room temperature to effect spontaneous annealing (step 3), as shown in FIG. 3.
FIG. 4 schematically shows a conventional common plating apparatus including a plating unit for performing the above-described plating, and a removal unit, for example comprised of a bevel etching/back surface cleaning unit, for performing the above-described removal of a metal film (copper film) in the ineffective region of a substrate and cleaning of the substrate. This plating apparatus 10 includes a rectangular apparatus frame 14 and transport boxes 12, detachably mounted to the apparatus frame 14, each housing substrates, e.g. substrates W having a seed layer 7, shown in FIG. 1A. Inside the apparatus frame 14 are disposed a stage 16, four plating units 18, two bevel etching/back surface cleaning units (removal units) 20, and two transport robots 22, 24 as transport devices.
According to the plating apparatus 10, substrates, e.g. the substrates W having a seed layer 7, are carried one by one by the transport robot 22 from a corresponding transport box 12 into the apparatus frame 14, and each substrate is transported to one of the plating units 18, where the substrate is plated. The substrate after plating is transported to one of the bevel etching/back surface cleaning units 20, where removal, by etching, of e.g. a copper film deposited in an ineffective region of the substrate and subsequent cleaning and, according to necessity, cleaning of a back surface of the substrate are performed, followed by drying. Thereafter, the substrate is returned by the transport robot 22 to an original position in the transport box 12.
FIG. 5 schematically shows a conventional common annealing apparatus (crystal stabilization apparatus) having an annealing unit (crystal stabilization unit) for performing crystal stabilization processing of a metal film by the above-described annealing (heating). This annealing apparatus 26 includes a rectangular apparatus frame 28 and transport boxes 12, detachably mounted to the apparatus frame 28, each housing substrates, e.g. substrates having a copper film 6 which has been deposited by the above plating apparatus 10, such as shown in FIG. 1B. Inside the apparatus frame 28 are disposed two annealing units 30 and a transport robot 32 as a transport device.
According to the annealing apparatus 26, the substrates after plating, for example, are carried one by one by the transport robot 32 from a corresponding transport box 12 into the apparatus frame 28, and each substrate is transported to one of the annealing units 30, where the substrate is subjected to annealing. The substrate after annealing is returned by the transport robot 32 to an original position in the transport box 12.
FIG. 6 schematically shows a conventional common CMP apparatus having a CMP unit for performing the above-described chemical-mechanical polishing (CMP). This CMP apparatus 34 includes a rectangular apparatus frame 36 and transport boxes 12, detachably mounted to the apparatus frame 36, each housing e.g. substrates which have been annealed in the above annealing apparatus 26. Inside the apparatus frame 36 are disposed two CMP units 46, each including a top ring 38, a turntable (polishing table) 40, a dresser 42 and a loader 44, for polishing a substrate by pressing the substrate held by the top ring 38 against a polishing surface (upper surface) of the turntable 40 while moving the substrate and the turntable 40 relative to each other. There are also disposed two stages 48, two scrub cleaning units 50 for performing scrub cleaning, two cleaning/drying units 52 for performing rinsing (cleaning) with pure water and spin-drying, and three transport robots 54, 56, 58 as transport devices inside the apparatus frame 36.
According to the CMP apparatus 34, the substrates after annealing are carried one by one by the transport robot 54 from a corresponding transport box 12 into the apparatus frame 36, and each substrate is transported to one of the CMP units 46, where the substrate is subjected to chemical-mechanical polishing (CMP). The substrate after CMP is transported to one of the scrub cleaning units 50 for scrub cleaning of the substrate, and this cleaned substrate is transported to one of the cleaning/drying units 52 for rinsing with pure water and spin-drying of the substrate. Thereafter, the substrate is returned by the transport robot 54 to an original position in the transport box 12.
A composite apparatus 60 which combines the above-described plating apparatus 10 and annealing apparatus 26, as shown in FIG. 7, is known. As shown in FIG. 7, annealing unit 30 is provided beside the above-described plating apparatus 10 and they communicate with each other through a passage 62, so that after plating and a subsequent bevel etching/back surface cleaning of a substrate, annealing of the substrate can be performed.
For formation of metal interconnects in e.g. an LSI, it is a conventional practice to employ the above-described plating apparatus 10, annealing apparatus 26, CMP apparatus 34, and the like in a proper combination. With progress toward finer metal interconnects and emergence of new interlayer dielectric materials, many unexpected technical problems have arisen. Such technical problems have not surfaced in conventional interconnect formation processes which use, as interlayer dielectric materials, existing materials such as SiO2, SiOF, SiOC, SiLK, and the like. The following is a description of the technical problems.
Porous materials (porous low-k materials), which have a lower dielectric constant k than conventional insulating materials, are attracting attention as promising next-generation interlayer dielectric materials. Such materials, because of their internal porous structure, generally have lower mechanical strength and thus are weaker than the conventional interlayer dielectric materials. Use of such a porous material can cause peel-off or separation of an interlayer dielectric or copper interconnects during chemical-mechanical polishing (CMP), leading to an interconnect breakage or a short circuit. Many factors may be involved in these problems or drawbacks, such as a shortage of mechanical strength of the interlayer dielectric itself, poor adhesion at an interface between an insulating film and a different material, interfacial peeling caused by a difference in expansion/contraction upon a thermal change between different materials, for example, a porous low-k material and a metal, and the like.
In order to solve or minimize the problems, it is most desirable to provide a low-k material with enhanced strength. Other approaches are directed to technical improvements, such as lowering of stress applied to a substrate in a chemical-mechanical polishing process (e.g. low-load polishing), reduction of an expansion/contraction difference between materials in a metal crystal stabilization process, minimization of a thickness of a plated film in a plating process, reduction of a level difference after plating, and the like. These approaches, however, have their own difficult problems that would take a long time to solve.